module	Uart_rx_module
(
	clk_100,rst,uart_rx,rx_bps_flag,
	out_rx_data,rx_bps_start
);

input		clk_100;
input		rst;
input		uart_rx;
input		rx_bps_flag; //中间采样点

output	rx_bps_start;//接收端口的波特率时钟启动信号
output	[7	: 0]	out_rx_data;//uart最终接收的数据

reg	[1	:	0]		detect_edge;  //记录uart的开始脉冲
wire	[1	:	0]		detect_edge_n;//detect_edge的下一个状态

reg					negedge_reg;//下降沿标志
wire					negedge_reg_n;//下降沿标志的下一个状态

reg					rx_bps_start;//接收端口波特率时钟启动信号
reg					rx_bps_start_n;//下一个状态

reg	[3	:	0]		bit_cnt;
reg	[3	:	0]		bit_cnt_n;

reg	[7	:	0]		shift_data;
reg	[7	:	0]		shift_data_n;

reg	[7	:	0]		out_rx_data;
reg	[7	:	0]		out_rx_data_n;

always	@	(posedge clk_100 or negedge rst)
begin
	if(!rst)
		detect_edge <= 2'b11;
	else
		detect_edge <= detect_edge_n;
end

assign	detect_edge_n = {detect_edge[0],uart_rx};

always	@	(posedge clk_100 or negedge rst)
begin
	if(!rst)
		negedge_reg <= 1'b0;
	else
		negedge_reg <= negedge_reg_n;
end

assign	detect_reg_n = (detect_edge == 2'b10)?1'b1:1'b0;

always @ (posedge clk_100 or negedge rst)
begin
	if(!rst)
		rx_bps_start <= 1'b0;
	else
		rx_bps_start <= rx_bps_start_n;
end

always	@	(*)
begin
	if(negedge_reg)
		rx_bps_start_n = 1'b1;
	else if(bit_cnt == 4'd9)
		rx_bps_start_n = 1'b0;
	else
		rx_bps_start_n = rx_bps_start;
end

always	@	(posedge clk_100 or	negedge	rst)
begin
	if(!rst)
		bit_cnt <= 4'b0;
	else
		bit_cnt <= bit_cnt_n;
end

always	@	(*)
begin
	if(rx_bps_flag)
		bit_cnt_n = bit_cnt + 1'b1;
	else if(bit_cnt == 4'd9)
		bit_cnt_n = 1'b0;
	else
		bit_cnt_n = bit_cnt;
end

always	@	(posedge clk_100 or negedge rst)
begin
	if(!rst)
		shift_data <= 8'b0;
	else
		shift_data <= shift_data_n;
end

always	@	(*)
begin
	if(rx_bps_flag)
		shift_data_n = {uart_rx,shift_data[7:1]};
	else
		shift_data_n = shift_data;
end

always	@	(posedge clk_100 or	negedge rst)
begin
	if(!rst)
		out_rx_data <= 8'b0;
	else
		out_rx_data <= out_rx_data_n;
end

always	@	(*)
begin
	if(bit_cnt == 4'd9)
		out_rx_data_n = shift_data;
	else
		out_rx_data_n = out_rx_data;
end

endmodule
